The goal of integrated circuit packaging is to provide more reliable circuits with lower costs, faster speed, and higher density. In the future, for the integrated circuit packaging, the integration density of various electronic components will be constantly improved by reducing the minimum feature size. Currently, the advanced packaging methods include wafer level chip scale packaging (WLCSP), fan-out wafer level packaging (FOWLP), flip chips (FC), package on package (POP), and the like.
The FOWLP is a wafer level built-in chip packaging method, and is one of the advanced packaging methods having a relatively large amount of input/output (I/O) ports and good integration flexibility. Compared with conventional wafer level packaging, the FOWLP has unique advantages: {circle around (1)} The I/O spacing is flexible and does not rely on chip sizes. {circle around (2)} Only effective dies are used, which improves the product yield. {circle around (3)} The FOWLP has a flexible three dimensional (3D) package path, that is, any array pattern may be formed on the top. {circle around (4)} The electrical performance and thermal performance are good. {circle around (5)} The FOWLP may be applied in high frequency applications. {circle around (6)} High-density wiring is easy to implement on a redistribution layer (RDL).
In an existing fan-out package structure having an antenna, the antenna and a semiconductor chip are packaged and connected to each other by using a substrate. Moreover, an electrical connection structure between various metal layers in the package structure is formed by using an exposing electroplating process. The fan-out package structure having an antenna has the following problems: the package structure has a relatively large size and relatively high costs, and the performance of the package structure is affected due to a relatively large height of the electrical connection structure.